Dr. Anirban Sengupta

Ph.D., MASc., P.Eng (registered), Ontario

Assistant Professor
(appointment approved for Associate Professor)

'Sir Visvesvaraya' Faculty Research Fellow (Awarded by MeitY)

Principal Investigator, Lab on Behavioural Synthesis of Digital IP core
Computer Science & Engineering
Indian Institute of Technology (I.I.T) Indore

 

  • Associate Editor, IEEE Transactions on Aerospace & Electronic Systems (TAES)
  • Guest Editor: IEEE Transactions on VLSI Systems
  • Associate Editor: IET Journal on Computer & Digital Techniques
  • Associate Editor: IET Journal on Computer & Digital Techniques
  • Executive Editor: IEEE Consumer Electronics (CE-M)
  • Associate Editor: IEEE Access Journal
  • Associate Editor: IEEE VLSI Circuits & Systems Letter
  • Guest Editor: IEEE Transactions on Consumer Electronics
  • Guest Editor: IEEE Access Journal
  • Columnist: IEEE Consumer Electronics (CE-M)
  • Editorial Board Member: Elsevier Microelectronics Journal
  • Program Chair: 15th IEEE International Conference on Information Technology (ICIT)
  • Program Chair: 36th IEEE International Conference on Consumer Electronics (ICCE) 2018, Las Vegas, USA
  • Program Chair: 3rd IEEE iNIS 2017, India

Highlights

  • 107 Publications & Patents (major contributions in IEEE Transactions, IEEE Journals, IEEE magazines, IET Journals, Elsevier Journals and US Patents) in the area of EDA- CAD for High Level Synthesis (domain of EDA and CAD-VLSI)
  • Holds 10 Editorial Positions in reputed recognized Transactions/Journals of IEEE, IET and Elsevier.
  • Awarded highest rating "Excellent" by expert committee of Department of Science & Technology (DST) based on the performance (output) in externally funded project in 2017.
  • Awarded by IEEE for research contributions in IEEE Access Journal in advancing engineering profession in July 2016. 
  • Holds 11 Patents in the area of EDA - CAD for High Level Synthesis.
  • Awarded external grant by DST for sponsored project in March 2013.  
  • Offered ‘Honorary Chief Scientist’ position in VividSparks IT Solutions Pvt Ltd. in July 2016. 
  • 2 Patents accepted for commercialization/integration into system on chip products of VividSparks IT Solutions Pvt Ltd. in July 2016. 
  • Graduated 2 Ph.D.s as thesis supervisor from IIT Indore.

 

 

 

 

 

 

 

 

 

                                                            

My Source of Mental and Physical Strength: I am highly thankful to GOD for always Blessing me as well as indebted to my parents for their support.

 

 

 Editorial Positions

 

 

 

 

Awards  

 

Sponsored Project (Govt. Grant)  

 

 

 Funding generated from my Patents

 

 

 

Education/Background

 

Research Talks/Presentations

 

Research Facilities (HW & SW) 

 

 

 

Bio: Dr. Anirban Sengupta is working in the Discipline of Computer Science and Engineering at Indian Institute of Technology (I.I.T) Indore, here he directs the research lab on ‘Behavioural Synthesis of Digital IP core ’. He holds a Ph.D. & M.A.Sc.  in Electrical & Computer Engineering from Ryerson University, Toronto (Canada) and is a registered Professional Engineer of Ontario (P.Eng.). He also holds a B.Tech degree from West Bengal University of Technology, India. In the past, he was also affiliated with Indian Institute of Science (IISc) Bangalore as a visiting research scholar.He holds an external affiliation as 'Honorary Chief Scientist' at VividSparks IT Solutions Pvt Ltd, besides his regular affiliation at IIT-I. One of his his work has been bestowed with "Best Research Paper Award 2017" by Indian Institute of Technology Indore.
His research interest includes Optimization during Design Space Exploration for Hardware Accelerators, High Level Synthesis, Fault Secured High Level Synthesis, Trojan Security Aware HLS, Hardware Trust in High Level Synthesis, IP core Protection during HLS, Evolutionary Computing during HLS as well as Physical Design using CAD. His research/sponsored projects are funded by Department of Science & Technology (Science & Engineering Research Board), Govt. of India as well as supported by Intel Corporation and Department of Electronics & IT (DEITY), Govt. of India. He has around 107 Publications & Patents which include Journals, Patents and Invited Book Chapters from IEEE, IET, Elsevier, Springer and USPTO/CIPO/IPO. He is owner 11 Patents (granted/published/pending).  In the past, his Patents generated funding from Ontario Center of Excellence (OCE), Canada. He had performed industry interactive research extensively for more than 2 years with Calypto, Bluespec, BEECube, Huawei Canada during development of his Ryerson Design Space Exploration Tool arising from his Patent. For his excellence in doctoral research, he has been awarded/nominated by Ministry of Training, Colleges and Universities, Ontario for multiple years through OGS as well as by Ryerson University through GREA, RGA and NSERC ICA for consecutive years. 'Awarded highest rating "Excellent" by expert committee of Department of Science & Technology (DST) based on the performance (output) in externally funded project in 2017.
He currently serves in Editorial positions of 10 IEEE Transactions/Journals, Elsevier, & IET Journals including IEEE Transactions on Aerospace and Electronic Systems (TAES), IEEE Transactions on VLSI Systems, IEEE Aceess Journal, IET Journal on Computer & Digital Techniques, Elsevier Microelectronics Journal, IEEE Consumer Electronics Magazine, IEEE VLSI Circuits & Systems Letter. He further serves as Guest Editor of IEEE Transactions on Consumer Electronics, IEEE Transactions on VLSI Systems and IEEE Access Journals. He is a regular reviewer of IET Journal on Computers and Digital Techniques, IEEE Transactions on VLSI, Elsevier Journal on Swarm and Evolutionary Computation, Elsevier Journal on Applied Soft Computing and Elsevier Journal on Expert Systems. He regularly serves as a member of the Technical Program Committee of IEEE-CS ISVLSI, ACM GLVLSI, IEEE CCECE and IEEE ICIT. He has supervised 4 Ph.D. candidates (2 completed and 2 pursuing) and 6 RA/B.Eng. students, many of whom are/were placed in industries such as Cadence, Snapdeal, Microsoft etc or pursuing research in renowned universities such as Stanford, UCSD etc.

My following research papers have featured as 'Top 50 Popular Articles' from IEEE Periodicals:

1. "TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal
Loop Unrolling Factor during High Level Synthesis"
(Top 50 list in IEEE Transactions on CAD of Integrated Circuit & Systems in Aug 2016)


2. "Hardware Security of CE Devices: Threat Models and Defence against IP Trojans and IP Piracy"
(Top 50 list in IEEE Consumer Electronics Magazine from Dec 2016 - Jan 2017)


3. "Design Flow of a Digital IC: The role of digital IC/SOC design in CE products"
(Top 50 list in IEEE Consumer Electronics Magazine from June 2016 - Nov 2016)


4. "Intellectual Property Cores: Protection of IP-Core Designs for CE Products"
(Top 50 list in IEEE Consumer Electronics Magazine from April 2016 - July 2016)


5. "Evolution of IP Design Process in Semiconductor/EDA Industry"
(Top 50 list in IEEE Consumer Electronics Magazine from April 2016 - July 2016)