Research Publications: 125

Breakup:
Peer-reviewed Journals/Patents/Invited Book Chapters: 66
Peer-reviewed /Conference publications: 52
Thesis/Industry report: 6
----------------------------------------------------------------------------------------------------------------

I. PATENTS

  1. Anirban Sengupta, "Embedding Watermark based on Multi-Variable Signature Encoding at Behaviour Level for Reusable IP Core Protection", Patent 4466/MUM/2015, July 11, 2017. (Status: Published)
  2. Anirban Sengupta, "Design Space Exploration Of An Optimized Hardware Trojan Detectable/Secured Datapath During High Level Synthesis", Patent#1666/MUM/2015, Â 2015 (Status: Published)
  3. Anirban Sengupta," Design Space Exploration of Optimal Kc-Cycle Transient Fault Secured Datapath System with Intelligent Cut Insertion", Patent No. 63/MUM/2015, 2015 (Status: Published).
  4. Anirban Sengupta "Design Space Exploration System and Method Thereof Using a Bacterial Foraging Optimization Mechanism", Patent No. 2440/MUM/2014, 2015 (Status: Published).
  5. Anirban Sengupta "Design Space Exploration of Optimal k-Cycle Transient Fault Tolerant Datapath Based on Multi-Objective Power-Performance Tradeoff", Patent No. 2456/MUM/2014, 2015 (Status: Published).
  6. Anirban Sengupta "Method and System for Automatic Fault Recovery and True Output Extraction during High Level Synthesis", Patent No. 2478/MUM/2014, 2015.
  7. Anirban Sengupta "Improved Schedule Delay Estimation Process for Datapath during High Level Synthesis of Application Specific Processors", Patent No. 2482/MUM/2014, 2015, (Status: Published).
  8. Anirban Sengupta (co-inventor: Reza Sedaghat),"System and Method for Development of System Architecture", US Patent by United Sates Patent and Trademark Office (USPTO), Patent no. US 8,826,199 B2, Sep 2014.
  9. Anirban Sengupta (co-inventor: Reza Sedaghat),"System and methodology for development of a system architecture using optimization parameters", US Patent by United Sates Patent and Trademark Office (USPTO), Patent no. US 8,397,204, March 12, 2013. (Used/Cited in US Patent of Science & Technology Corporation, University of New Mexico). 
  10. Anirban Sengupta (co-inventor: Reza Sedaghat),"System and Method for Development of System Architecture using optimization parameters", Canadian Patent by Canadian Intellectual Property Office (CIPO), Patent # CA2726091A1, June 21, 2012.
  11. Anirban Sengupta (co-inventor: Reza Sedaghat),"System and Methodology for Development of System Architecture", Canadian Patent by Canadian Intellectual Property Office (CIPO), Patent # CA2741253A1, Nov 27, 2012.

 

II. JOURNALS AND INVITED BOOK CHAPTERS

Yr: 2018

  1. Anirban Sengupta, Deepak Kachave "Forensic Engineering for Resolving Ownership Problem of Reusable IP Core generated during High Level Synthesis", Elsevier Journal on Future Generation Computer Systems, Accepted, Aug 2018 (Impact Factor ~ 4.8).
  2. Anirban Sengupta, Dipanjan Roy "Framework for IP based Lossless Image Compression for Camera Systems", IEEE Consumer Electronics, Accepted, 2018 (Impact Factor ~ 1.15).

 

Yr: 2017

  1. Anirban Sengupta, Dipanjan Roy, Saraju P Mohanty, "Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Accepted, 2017 Impact factor ~ 2
  2. Anirban Sengupta, Dipanjan Roy "Protecting an Intellectual Property Core during Architectural Synthesis using High-Level Transformation Based Obfuscation" IET Electronics Letters, Volume: 53, Issue: 13, June 2017, pp. 849 - 851
  3. S. P. Mohanty, A. Sengupta, P. Guturu, and E. Kougianos, "Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection", IEEE Consumer Electronics, Volume 7, Issue 3, July 2017, pp. 83--91. Impact factor ~ 1.15
  4. Anirban Sengupta, Deepak Kachave "Particle Swarm Optimisation Driven Low Cost Single Event Transient Fault Secured Design during Architectural Synthesis (Invited Paper)" IET Journal of Engineering, Dec 2017, doi: 10.1049/joe.2016.0378.
  5. Anirban Sengupta, Sandip Kundu "Securing IoT Hardware: Threat models and Reliable, Low-power Design Solutions", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Accepted, Jan 2017. Impact factor ~ 1.12
  6. Anirban Sengupta"Hardware Vulnerabilities and its Effect on CE Devices: Design-for-Security against Trojan", IEEE Consumer Electronics, Volume: 6, Issue: 3, July 2017, pp. 126 - 133. Impact factor ~ 1.15.
  7. Anirban Sengupta, Dipanjan Roy "Anti-Piracy aware IP Chipset Design for CE Devices: Robust Watermarking Approach", IEEE Consumer Electronics, Volume: 6, Issue: 2, April 2017, pp. 118 - 124. Impact factor ~ 1.15
  8. Anirban Sengupta, "Hardware Security of CE Devices: Threat Models and Defence against IP Trojans and IP Piracy", IEEE Consumer Electronics, Jan 2017, Volume: 6, Issue: 1 ,pp. 130 - 133. Impact factor ~1.15
  9. Anirban Sengupta, Deepak Kachave "Low Cost Fault Tolerance against kc-cycle and km-unit Transient for Loop Based Control Data Flow Graphs during Physically Aware High Level Synthesis", Elsevier Journal on Microelectronics Reliability, Volume 74, July 2017, pp. 88-99. Impact factor ~ 1.6
  10. Anirban Sengupta, Santosh Rathlavat, Pallabi Sarkar, Mrinal Kanti Naskar "A Firefly Algorithm Approach for Hardware Accelerators in CE Devices", IEEE Consumer Electronics, Accepted, October 2017. Impact factor ~ 1.15
  11. Anirban Sengupta, Madhavi Ganapathiraju, "Audio & Video Technologies of Consumer Electronics Devices", IEEE Consumer Electronics, Accepted, October 2017. Impact factor ~ 1.15
  12. Dipanjan Roy, Anirban Sengupta "Low Overhead Symmetrical Protection of Reusable IP Core using Robust Fingerprinting and Watermarking during High Level Synthesis", Elsevier Journal on Future Generation Computer Systems, Volume 71, June 2017, pp. 89–101. Impact factor ~4.8
  13. Anirban Sengupta, Dipanjan Roy "Automated Low Cost Scheduling Driven Watermarking Methodology for Modern CAD High-Level Synthesis Tools" Elsevier Journal of Advances in Engineering Software, Volume 110, August 2017, pp 26-33. Impact factor ~3
  14. Anirban Sengupta "Mathematical Models for Latency Estimation of Loop Unrolled and Loop Pipelined CDFGs during High Level Synthesis", IEEE VLSI Circuits & Systems Letter, Volume 2, Issue 2, 2017, pp. 15 - 18.

Yr: 2016

  1. Anirban Sengupta, Saumya Bhadauria, Saraju P Mohanty "TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal Loop Unrolling Factor during High Level Synthesis", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 36, Issue: 4, April 2017, pp. 655 – 668. Impact factor ~1.2
  2. Anirban Sengupta, Peter Corcoran "Advances in Smart Robust Low Cost Hardware System Design for Digital Consumer Electronics", IEEE Transactions on Consumer Electronics, Accepted, special section, July 2016 . Impact factor ~1.1
  3. Anirban Sengupta, Saumya Bhadauria, "Exploring Low Cost Optimal Watermark for Reusable IP Cores during High Level Synthesis" , IEEE Access Journal, Invited paper, Volume:4, Issue: 99, pp. 2198 - 2215, May 2016 . Impact factor ~ 3.22
  4. Anirban Sengupta, F. Lombardi, S.P Mohanty, M. Zwolinski, "Security and Reliability Aware System Design for Mobile Computing Systems", IEEE Access Journal, Volume: 4, 2016, pp. 2976 - 2980 . Impact factor ~3.22
  5. Anirban Sengupta, Saumya Bhadauria "IP core Protection of CDFGs using Robust Watermarking during Behavioral Synthesis Based on User Resource Constraint and Loop Unrolling Factor", IET Electronics Letters, Vol. 52 No. 6 pp. 439-441, March 2016 .Impact factor ~1.1
  6. Anirban Sengupta, Saumya Bhadauria, and Saraju P. Mohanty, "Low Cost Security Aware High Level Synthesis Methodology", IET Journal on Computers & Digital Techniques (CDT), Volume: 11, Issue: 2, 3 2017, pp. 68 - 79. Impact factor ~0.6
  7. Anirban Sengupta "Resilient Soft IP-Core Design Against Terrestrial Transient Faults for CE Products", IEEE Consumer Electronics, Volume: 5, Issue: 4, Oct. 2016, pp. 129 - 131. Impact factor ~1.1
  8. Deepak Kachave, Anirban Sengupta, “Integrating Physical Level Design and High Level Synthesis for Simultaneous Multi-Cycle Transient and Multiple Transient Fault Resiliency of Application Specific Datapath Processors”, Elsevier Journal on Microelectronics Reliability, Volume 60, Pages 141-152, May 2016 .Impact factor ~1.6
  9. Anirban Sengupta, "Design Flow of a Digital IC for CE Products", IEEE Consumer Electronics, April 2016,Vol.5, Issue: 2, pp.58 - 62. Impact factor ~1.15
  10. Anirban Sengupta "Cognizance on Intellectual Property: A High-Level Perspective", IEEE Consumer Electronics, Vol. 5, Issue 3, pp. 126 - 128, 2016. Impact factor ~1.15
  11. Anirban Sengupta "Evolution of IP Design Process in Semiconductor/EDA Industry", IEEE Consumer Electronics, April 2016, Vol.5, Issue: 2, pp.123 - 126. Impact factor ~1.15
  12. Anirban Sengupta, Saraju P.Mohanty "High-Level Synthesis of Digital Circuits in the Nanoscale, Mobile Electronics Era", IET Book: Nano-CMOS and Post-CMOS Electronics: Circuits and Design, (Eds: Saraju P Mohanty& Ashok Srivastava), Invited Book Chapter, e-ISBN: 9781785610004, pp: 219 - 261, June 2016
  13. Anirban Sengupta, Saumya Bhadauria,"Optimized Hardware Design for Trojan Security at Behavioral Level for Loop Based Applications", Elsevier Journal on VLSI Integration, Jan 2016. Impact factor ~1

Yr: 2015

  1. Anirban Sengupta "Protection of IP-Core Designs for CE Products", IEEE Consumer Electronics, Vol 5, pp. 83- 89, Dec 2015. Impact factor ~1.15
  2. Anirban Sengupta "Exploration of kc-cycle Transient Fault Secured Datapath and Loop Unrolling Factor for Control Data Flow Graphs during High Level Synthesis", IET Electronics Letters, volume 51, Issue 7, Feb 2015, pp. 562 - 564. Impact factor ~1.1
  3. Vipul Kumar Mishra, Anirban Sengupta, "Swarm Inspired Exploration of Architecture and Unrolling Factors for Nested Loop Based Application in Architectural Synthesis", IET Electronics Letters, Volume 51,Issue: 2, Jan 2015, pp. 157 - 159. Impact factor ~1.1
  4. Anirban Sengupta, Saumya Bhadauria, Adaptive Bacterial Foraging Driven Datapath Optimization: Exploring Power-Performance Tradeoff in High Level Synthesis, Elsevier Journal on Applied Mathematics & Computation, Vol. 269, pp. 265 - 278 , 2015. Impact factor ~1.73
  5. Anirban Sengupta, Saumya Bhadauria, "Bacterial Foraging Driven Exploration of Multi Cycle Fault Tolerant Datapath based on Power-Performance Tradeoff in High Level Synthesis", Elsevier Journal on Expert Systems With Applications, Volume 42, Jan 2015, pp. 4719 - 4732 . Impact factor ~3.92
  6. Anirban Sengupta, Reza Sedaghat “Swarm Intelligence Driven Design Space Exploration of Optimal k-Cycle Transient Fault Secured Datapath during High Level Synthesis Based on User Power-Delay Budget", Elsevier Journal on Microelectronics Reliability, Volume 55, Issue 6, May 2015, pp. 990-1004, March 2015. Impact factor ~1.6
  7. Anirban Sengupta, Saumya Bhadauria, "Automated Design Space Exploration of Multi-Cycle Transient Fault Detectable Datapath based on Multi-Objective User Constraints for Application Specific Computing", Elsevier Journal on Advances in Engineering Software, Volume 82, April 2015, pp. 14- 24. Impact factor ~3
  8. Saumya Bhadauria, Anirban Sengupta, ”Multi-Cycle Single Event Transient Fault Security Aware MO-DSE for Single loop CDFGs in HLS”, IEEE VLSI Circuits & Systems Letter, Vol. 1, Issue 2, Oct 2015, pp. 2-8.
  9. Anirban Sengupta "Protection of Reusable IP core at Architectural Level", IEEE VLSI Circuits & Systems Letter, Vol. 1, Issue 2, Oct 2015, pp. 14 - 17.
  10. Anirban Sengupta, Vipul Kumar Mishra, "A Methodology for Comprehensive Schedule Delay Estimation during Design space Exploration in Architectural Synthesis", IEEE VLSI Circuits & Systems Letter, Volume 1, Issue 1, April 2015, pp. 2 - 8.
  11. Anirban Sengupta, VK Mishra. "Simultaneous Exploration of Optimal Datapath and Loop Based High level Transformation during Area-Delay Tradeoff in Architectural Synthesis Using Swarm Intelligence", IOS Press - Journal of Knowledge-Based and Intelligent Engineering Systems, Volume 19, April 2015, pp. 47 - 61. Impact factor ~0.6

 Yr: 2014

  1. Anirban Sengupta, Vipul Kumar Mishra "Automated Exploration of Datapath and Unrolling Factor during Power-Performance Tradeoff in Architectural Synthesis Using Multi-Dimensional PSO Algorithm", Elsevier Journal on Expert Systems With Applications, Volume 41, Issue 10, August 2014,pp. 46914703 . Impact factor ~3.92
  2. Vipul Kumar Mishra, Anirban Sengupta "MO-PSE: Adaptive Multi Objective Particle Swarm Optimization Based Design Space Exploration in Architectural Synthesis for Application Specific Processor Design", Elsevier Journal on Advances in Engineering Software, Volume 67, January 2014, pp. 111124 . Impact factor ~3<
  3. Anirban Sengupta "Design Space Exploration of Datapath (Architecture) in High Level Synthesis for Computation Intensive Applications", Springer Book volume: Application of Evolutionary Algorithms for Multi-Objective Optimization in VLSI and Embedded Systems, Print ISBN: 978-81-322-1957-6, August 2014, pp. 93 - 111
  4. Anirban Sengupta "Design Flow from Algorithm To RTL using Evolutionary Exploration Approach", Springer Book volume: Application of Evolutionary Algorithms for Multi-Objective Optimization in VLSI and Embedded Systems, Print ISBN: 978-81-322-1957-6, August 2014, pp. 113 - 123.
  5. Anirban Sengupta, Saumya Bhadauria "Exploration of Multi-Objective Tradeoff During High Level Synthesis Using Bacterial Chemotaxis and Dispersal", Elsevier Journal on Procedia Computer Science, Sep 2014, Volume. 35, Issue. C, pp. 63 72.
  6. Anirban Sengupta, Reza Sedaghat, Vipul Kumar Mishra, "Execution Time Area Tradeoff in GA using Residual Load Decoder: Integrated Exploration of Chaining Based Schedule and Allocation in HLS for Hardware Accelerators, Journal of Facta Universitatis: Series Electronics and Energetics, Volume 27, No. 2,pp. 235 249,June 2014. Impact factor ~0.6
  7. Reza Sedaghat, Anirban Sengupta, "Rapid Exploration of Cost-Performance Tradeoffs using Dominance Effect during Design of Hardware Accelerators, Journal of Facta Universitatis: Series Electronics and Energetics, Vol. 27, No. 3 , Sep 2014, pp. 317 - 328. Impact factor ~0.6

 Yr: 2012

  1. Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar "Rapid Exploration of Integrated Scheduling and Module Selection in High Level Synthesis for Application Specific Processor Design", Elsevier Journal of Microprocessors and Microsystems", Volume36, Issue 4, Pages 303314, June 2012. Impact factor ~1.02
  2. Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, "A Multi Structure Genetic Algorithm for Integrated Design Space Exploration of Scheduling and Allocation in High Level Synthesis for DSP Kernels", Elsevier Journal of Swarm and Evolutionary Computation, Volume 7, December 2012, Pages 3546. Impact factor ~ 5.5

Yr: 2011

  1. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "Multi objective Efficient Design Space Exploration and Architectural Synthesis of an Application Specific Processor (ASP)", Elsevier Journal of Microprocessors and Microsystems, Volume 35, Issue 4, June 2011, pp. 392-404. Impact factor ~1.02
  2. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "Rapid Design Space Exploration by Hybrid Fuzzy Search Approach for Optimal Architecture determination of Multi Objective Computing Systems", Elsevier Journal of Microelectronics Reliability, Vol. 51, Issue 2, 2011, pp. 502-512. Impact factor ~1.6
  3. Anirban Sengupta, Reza Sedaghat, "A High Level Synthesis Design Flow from ESL to RTL with multi-parametric optimization objective", IETE Journal of Research, Volume 57, Issue 2, 2011, pp. 169-186. Impact factor ~0.2

Yr: 2010

  1. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "A High Level Synthesis design flow with a novel approach for Efficient Design Space Exploration in case of multi parametric optimization objective", Elsevier Journal of Microelectronics Reliability, Vol. 50, Issue 3, 2010, pp. 424-437. Impact factor ~1.6

Before 2010

  1. Anirban Sengupta and Pallabi Sarkar "Temperature-Tolerance Checking System", Electronics For You, Vol. 41, Issue no: 10, pp: 116-117, 2009.
  2. Pallabi Sarkar and Anirban Sengupta "Automated Alarm Circuits", Electronics For You, Vol.: 41, Issue no: 2, pp: 96-98, 2008.

 

III. REFEREED PEER-REVIEWED CONFERENCE PROCEEDINGS (Count # 52)

Yr: 2017

  1. Anirban Sengupta, Dipanjan Roy "Multi-Phase Watermark for IP Core Protection", Proc. 36th IEEE International Conference on Consumer Electronics (ICCE) 2018, Las Vegas, Accepted, Jan 2018
  2. Dipanjan Roy, Anirban Sengupta "Reusable Intellectual Property Core Protection for Both Buyer and Seller", Proc. 36th IEEE International Conference on Consumer Electronics (ICCE) 2018, Las Vegas, Accepted, Jan 2018
  3. Anirban Sengupta "Reliability and Performance Aware SoC solutions for IoT Framework", IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Accepted, June 2017.
  4. Anirban Sengupta "Architecture-Level Energy, Security, and Reliability Solutions for CE Digital Hardware", 36th IEEE International Conference on Consumer Electronics (ICCE), Accepted, Las Vegas, March 2017.
  5. Anirban Sengupta, Dipanjan Roy “Mathematical Validation of 2D HWT based Lossless Image Compression for CE applications”, Proc. IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Accepted, Dec 2017.
  6. Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar “A Firefly Algorithm Driven Approach for High Level Synthesis”, Proc. IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Accepted, Dec 2017.
  7. Deepak Kachave, Anirban Sengupta, Shubha Neema, Sri Harsha “Reliability and Threat analysis of NBTI Stress on DSP cores”, Proc. IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Accepted, Dec 2017.
  8. Vipul Mishra, Anirban Sengupta “Comprehensive Operation Chaining Based Schedule Delay Estimation during High Level Synthesis”, Proc. IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Accepted, Dec 2017.

Yr: 2016

  1. Deepak Kachave, Anirban Sengupta "Protecting Ownership of Reusable IP Core Generated during High Level Synthesis", Proc. IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Dec 2016, pp. 80 - 82
  2. Anirban Sengupta, Saumya Bhadauria, Saraju Mohanty "Embedding Low Cost Optimal Watermark During High Level Synthesis for Reusable IP Core Protection", Proc. of 48th IEEE Int'l Symposium on Circuits & Systems (ISCAS), Montreal, May 2016, pp. 974 - 977.
  3. Anirban Sengupta, Deepak Kachave "Generating Multi-Cycle and Multiple Transient Fault Resilient Design during Physically Aware High Level Synthesis", Proc. 15th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, July 2016, pp. 75 - 80
  4. Saumya Bhadauria, Anirban Sengupta," A High Level Synthesis Approach for Exploring Low Cost kc-cycle Transient Fault Secured Solution", 21st Asia South Pacific-Design Automation Conference (ASP-DAC), Accepted, Jan 2016.

Yr: 2015

  1. Anirban Sengupta, Saumya Bhadauria "Untrusted Third Party Digital IP cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis",25th IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI), Pennsylvania, May 2015, pp. 167 - 172 (DOUBLE BLIND REVIEW).
  2. Anirban Sengupta, Saumya Bhadauria, "User Power-Delay Budget Driven PSO Based Design Space Exploration of Optimal k-cycle Transient Fault Secured Datapath during High Level Synthesis", Proceedings of 16th IEEE International Symposium on Quality Electronic Design (ISQED), California, USA, March 2015, pp. 289 - 292 (DOUBLE BLIND REVIEW). 
  3. Anirban Sengupta, Saumya Bhadauria, "Automated Design Space Exploration of Transient Fault Detectable Datapath Based on User Specified Power and Delay Constraints", Proceedings of 33rd VLSI - Design Automation & Test (VLSI - DAT) Taiwan, April 2015, pp. 1 - 4 (DOUBLE BLIND REVIEW).
  4. Anirban Sengupta, Vipul Kumar Mishra and Reza Sedaghat, "Exploration of Optimal Multi-Cycle Transient Fault Secured Datapath during High Level Synthesis based on User Area-Delay Budget", Proceedings of 28th IEEE Canadian Conference on Electrical & Computer Engineering (CCECE), Halifax, May 2015, pp. 69 - 74. 
  5. Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar, "GA Driven Integrated Exploration of Loop Unrolling Factor and Datapath For Optimal Scheduling of CDFGs During High Level Synthesis", Proceedings of 28th IEEE Canadian Conference on Electrical & Computer Engineering (CCECE), Halifax, May 2015, pp. 75 - 80.
  6. Anirban Sengupta “Reliability and Security Aware RTL/System Design” ,Special Session in IEEE iNIS 2015,Participants: Intel Corporation, Broadcom Corporation (USA), Pennsylvania State University (USA) and Indian Institute of Science, Proposal Accepted.
  7. Anirban Sengupta, Saumya Bhadauria, “Secure Information Processing during System level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS based on User Constraints”, Proceedings of IEEE iNIS 2015 Special Session, Dec 2015, pp. 1 - 6.

Yr: 2014

  1. Anirban Sengupta, Vipul Kumar Mishra, "Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff ",Proceedings of 13th IEEE Computer Society Annual International Symposium on VLSI (ISVLSI),Florida, USA, July 2014, pp. 106 112 (DOUBLE BLIND REVIEW).
  2. Anirban Sengupta, Vipul Kumar Mishra , "Integrated Particle Swarm Optimization (i-PSO): An Adaptive Design Space Exploration Framework for Power-Performance Tradeoff in Architectural Synthesis", Proceedings of IEEE 15th International Symposium on Quality Electronic Design (ISQED 2014), Santa Clara, California, USA, March 2014, pp.60 - 67 (DOUBLE BLIND REVIEW).
  3. Anirban Sengupta, Vipul Mishra, "'Automated Parallel Exploration of Datapath and Unrolling Factor in High Level Synthesis using Hyper-Dimensional Particle Swarm Encoding'", Proceedings of 27th IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, May 2014, pp. 000069 - 000073.
  4. Anirban Sengupta, Saumya Bhadauria, "'Automated Exploration of Datapath in High Level Synthesis using Temperature Dependent Bacterial Foraging Optimization Algorithm'", Proceedings of 27th IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, May 2014, pp. 68- 73.
  5. Anirban Sengupta, Vipul Mishra," Multidimensional Encoding Based Evolutionary Exploration Approach: Adaptive Methodology for Parametric Trade-offs in High Level Synthesis for Control flow Graphs", Proceedings of 3rd IEEE CALCON, IEEE Kolkata, Nov 2014, pp. 43 - 46.
  6. Vipul Mishra, Anirban Sengupta, "PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis", Proceedings of 5th IEEE International Symposium on Electronic Design (ISED), Dec 2014, pp. pp. 10 - 14 (DOUBLE BLIND-REVIEW).
  7. Anirban Sengupta and Vipul Kumar Mishra, "Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality ", Proceedings of 13th IEEE International Conference on Information Technology, Dec 2014, pp. 281 - 286 (DOUBLE BLIND REVIEW).
  8. Anirban Sengupta and Saumya Bhadauria, "Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget", Proceedings of 13th IEEE International Conference on Information Technology, Dec 2014, pp. 345 - 350 (DOUBLE BLIND REVIEW).

 Yr: 2013

  1. Anirban Sengupta, Vipul Kumar Mishra,  Pallabi Sarkar, "Rapid Search of Pareto Fronts using D-logic Exploration during Multi-Objective Tradeoff of Computation Intensive Applications", Proceedings of IEEE 5th Asian Symposium on Quality Electronic Design (ASQED),Malaysia, August 2013, pp. 113-122.
  2. Vipul Mishra, Anirban Sengupta "Swarm Intelligence Driven Design Space Exploration: An Integrated Framework for Power-Performance Trade-off in Architectural Synthesis', Proceedings of 25th IEEE International Conference on Microelectronics (ICM 2013),Dec 2013, pp. 1 - 4.
  3. Anirban Sengupta, Vipul Mishra "D-logic Exploration: Rapid Search of Pareto Fronts during Architectural Synthesis of Custom Processors", Proceedings of IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2013), August 2013, Mysore, pp. 586 - 593.
  4. Anirban Sengupta "A Methodology for Self Correction Scheme Based Fast Multi Criterion Exploration and Architectural Synthesis of Data Dominated Applications", Proceedings of IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2013), August 2013, Mysore, pp.430 - 436.
  5. Anirban Sengupta "An Architecture Synthesis Tool for Rapid Multi-Objective Exploration and RTL Circuit Generation", ACM International Conference on Advances in Computing & Artificial Intelligence, Accepted, 2013.

 Yr: 2012

  1. Anirban Sengupta, Reza Sedaghat ,"Priority Function Driven Design Space Exploration in High Level Synthesis Based on Power Gradient Technique", Accepted in Student Forum of 17th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2012), Australia, pp: 25, 2012.

Yr: 2011

  1. Anirban Sengupta, Reza Sedaghat, "Integrated Scheduling, Allocation and Binding in High Level Synthesis using Multi Structure Genetic Algorithm based Design Space Exploration System", Proceedings of 12th IEEE/ACM International Symposium on Quality Electronic Design (ISQED 2011),Silicon Valley, California, USA, March 2011, pp. 486-494 (BLIND REVIEW).
  2. Anirban Sengupta, Reza Sedaghat, "A Hybrid Fuzzy Search Approach for Fast Design Space Exploration of Multi-Objective VLSI Systems", Accepted in the Student Forum of 16th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Japan, 2011,Paper ID: SF15.
  3. Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, "Integrated Scheduling, Allocation and Binding in High Level Synthesis for Performance-Area Tradeoff of Digital Media Applications", Proceedings of 24th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2011), Canada, May 2011, pp. 533-537.
  4. Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, "Priority Function based Power Efficient Rapid Design Space Exploration of Scheduling and Module Selection in High Level Synthesis", Proceedings of 24th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2011),Niagara, Canada, May 2011, pp. 538-543.
  5. Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta, "Power Gradient Based Design Space Exploration in High Level Synthesis for DSP Kernels", Proceedings of 23rd IEEE International Conference on Microelectronics (ICM), pp: 1 6, December 2011.
  6. Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar "Integrated Design Space Exploration Based on Power-Performance Trade-off using Genetic Algorithm", Proceedings of ACM International Conference on Advances in Computing and Artificial Intelligence, 2011, pp. 76-80.
  7. Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta, "Application Specific Processor vs. Microblaze Soft Core RISC Processor: FPGA Based Performance and CPR Analysis", Proceedings of ACM International Conference on Advances in Computing and Artificial Intelligence, 2011, pp.81-84.
  8. Summit Sehgal, Reza Sedaghat, Anirban Sengupta, "Automated Design Space Exploration for DSP Applications High Level Synthesis with Stability in Competition", Accepted for Publication, Proceedings of 2nd IEEE Latin American Symposium on Circuits and Systems (LASCAS), Columbia, February2011.

 Yr: 2010

  1. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "Rapid Design Space Exploration for multi parametric optimization of VLSI designs", Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, pp: 3164-3167, June 2, 2010.
  2. Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta, "A Framework for Fast Design Space Exploration using Fuzzy search for VLSI Computing Architectures", Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),Paris, France, 2010, pp: 3176-3179.  
  3. Anirban Sengupta, Reza Sedaghat, "Accelerated Exploration of Cost-Performance Tradeoffs for Multi Objective VLSI designs", Proceedings of 22nd IEEE International Conference on Microelectronics (ICM), 2010, pp. 100-103.
  4. Anirban Sengupta, Reza Sedaghat "Rapid Exploration of Power-Delay Tradeoffs using Hybrid Priority Factor and Fuzzy Search", In Proceedings of 22nd IEEE International Conference on Microelectronics (ICM), Egypt,2010, pp. 355-358. 
  5. Anirban Sengupta, Reza Sedaghat, "Fast Design Space Exploration for Multi Parametric Optimized VLSI and SoC Designs", Accepted in Student Forum of 15th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2010),Taiwan, 2010,ID: 26.
  6. Anirban Sengupta, Reza Sedaghat, "A Study on Architecture Optimization of the RISC Processor used for System-on Chip (SoC) design", In Proceedings of Research Innovation Symposium, Ryerson University, Canada, 2010, pp: 31.
  7. Summit Sehgal, Reza Sedaghat, Anirban Sengupta, "Fault Monitoring Transformer Reliability ASIC Design based on Ringing Effect Signature Analyzer", Proceedings of Research Innovation Symposium, Ryerson University, Canada, 2010, pp: 32.

Yr: 2009

  1. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "Hardware Efficient Design of speed optimized Power stringent Application Specific Processor", Proceedings of 21st IEEE International Conference on Microelectronics (ICM), Morocco, pp: 167-170, December 22, 2009.
  2. Summit Sehgal, Reza Sedaghat, Anirban Sengupta, Zhipeng Zeng, "Multi Parametric Optimized Architectural Synthesis of an Application Specific Processor", Proceedings of 14th IEEE International CSI Computer Conference (CSICC),2009, pp: 89-94.
  3. Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta, "A Novel Framework of Optimizing Modular Computing Architecture for multi objective VLSI designs", Proceedings of 21st IEEE International Conference on Microelectronics (ICM),Morocco, 2009, pp: 322-325.

 Yr: Before 2009

  1. Anirban Sengupta, Prasenjit Pal and S.K. Roy (Aug 1st & 2nd- 2008) "Problems Associated with CDMA Based Communication Systems Results and Discussions ",Accepted for poster presentation in the IEEE and IEI, the National Conference on "Device, intelligent systems and communication& networking, Paper No: CN_27. 

IV. THESIS/DISSERTATION (COUNT: 2)

  1. Anirban Sengupta, "A Fast Design Space Exploration Based on Priority Factor for a Multi Parametric Optimized High Level Synthesis Design Flow", Master of Applied Science (M.A.Sc) Thesis, Ryerson University, Toronto, Canada, 2010,(Nominated for Governor Generals Gold Medal in Canada for the Master’s Thesis). Available at Ryerson University, Toronto Library.
  2. Anirban Sengupta, "Rapid and Efficient Multi Objective Design Space Exploration in High Level Synthesis of Computation Intensive Applications", Doctor of Philosophy (Ph.D.) Thesis, Ryerson University, Toronto, Canada, 2012.

 

IV. TECHNICAL REPORTS FOR INDUSTRY/IP OFFICE (COUNT: 4)

  1. Anirban Sengupta, Reza Sedagha "Exploration Synthesizer: Design Automation Platform (DAP): Multi objective Design Space Exploration and Architectural Synthesis of Application kernels", No. of Pages: 14, Organization: Ryerson University (OPRAL Research Lab), MaRS Innovation, Aventis Consulting Group Inc and Venssa Technologies.
  2. Anirban Sengupta "Architectural Synthesis of Digital Systems (System Level Design)" , No. of pages: 39,Organization: Ryerson University (OPRAL Research Lab) (Co-author: Pallabi Sarkar)
  3. Anirban Sengupta "An ASIC Implementation Design Flow of Function Specific Processor- System Level, Logic Level and layout level Synthesis" , No. of pages: 67,Organization: Ryerson University (OPRAL Research Lab) (Co-author: Pallabi Sarkar)
  4. Anirban Sengupta "Performance Analysis of FPGA based ASP vs. Embedded Microblaze RISC Processor", No. of pages: 46,Organization: Ryerson University (OPRAL Research Lab), (Co-author: Pallabi Sarkar)